Field Effect Transistors (FET's) have become the dominant active device for Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) applications, because the integrated circuit FET is by nature a high impedance, high density, low power device. Much research and development activity has focused on improving speed and density of FETs, and on lowering the power consumption thereof.
As is well known to those having skill in the art there are two types of FET devices: the Insulated Gate FET (IGFET) and the Junction FET (JFET). Most present day integrated circuit technology employs the IGFET because of its simplified construction for integrated circuit applications. An IGFET typically comprises source and drain regions in a semiconductor substrate at a first surface thereof, and a gate region therebetween. The gate comprises an insulator on the first substrate surface between the source and drain regions, with a gate electrode or contact on the insulator. A channel is formed in the semiconductor substrate beneath the gate electrode, and the channel current is controlled by a voltage at the gate electrode.
In the most common configuration of an IGFET, an oxide layer is grown or otherwise formed on the first semiconductor surface, between the source and drain regions, and a metal or other gate electrode is formed on the oxide layer. This structure is commonly called a Metal Oxide Semiconductor Field Effect Transistor (MOS or MOSFET). The terms MOS and MOSFET are now used interchangeably with IGFET to include devices in which the insulator is a material other than an oxide (for example a nitride), and the gate electrode is a material other than metal (for example polysilicon). These terms will be used interchangeably herein.
Two types of channels may be provided in MOS devices. The first is referred to as an "induced channel", in which gate voltage induces a field in the substrate under the gate to thereby draw electrons (for a P-type substrate) into the region beneath the gate. As a result, this region changes conductivity type (e.g. P-type to N-type), and an induced channel is formed. The induced change of semiconductor material from one conductivity type to opposite conductivity type is called "inversion". Increasing gate voltage enhances the availability of electrons in the channel, so that an induced channel MOS device is referred to as operating in an "enhancement" mode.
The second type of channel is a "diffused channel" in which a channel having conductivity opposite that of the substrate is formed beneath the gate electrode. In such a device current flows between source and drain even in the absence of gate voltage. Decreasing gate voltage causes current to decrease as the diffused channel is depleted of carriers. Increasing gate voltage causes the gate current to increase as the diffused channel is enhanced. Accordingly, a diffused channel MOS device may operate in "enhancement" or "depletion" modes.
Enhancement mode (induced channel) devices are preferred for digital integrated circuit applications because these devices are off at zero gate voltage. Both enhancement and depletion mode devices have a threshold voltage associated therewith. The threshold voltage is the value of gate voltage needed to initiate device conduction. Threshold voltage is an important MOS characteristic and must be well controlled to provide satisfactory integrated circuit devices.
Unfortunately, the threshold voltage of known MOS devices typically varies as a function of the oxide thickness, the length of the channel, drain voltage, and the substrate doping concentration. Since each of these parameters can vary dramatically from one integrated circuit to another, very strict manufacturing tolerances (often referred to as "groundrules") must be provided to ensure device uniformity. However, strict manufacturing ground rules lower device yields. Moreover, since device dimensions and doping levels become more difficult to control as the devices become smaller, increases in device density and operating speed are difficult to obtain.
The threshold voltage of conventional MOS devices also varies as a function of device temperature. Unfortunately, device operating temperature varies considerably from one integrated circuit to another, depending upon the application. In fact, operating temperatures vary considerably within an integrated circuit, depending upon the duty cycle of the individual devices. MOS devices must be designed to operate properly despite the variation in threshold voltage with temperature. As such, lower performance and lower speed must be specified to ensure proper operation at all operating temperatures.
Many techniques have been proposed in an attempt to control threshold voltage while maintaining acceptable process groundrules; however such techniques cannot fully overcome the inherent variability of threshold voltage in the conventional FET structure. Other attempts have been made to improve the basic structure of the FET to provide improved characteristics. For example, a publication entitled A Normally-Off Type Buried Channel MOSFET For VLSI Circuits, by K. Nishiuchi et al. (IEDM Technical Digest, 1979, pages 26-29) discloses a buried channel MOSFET that uses a bulk region as a conducting channel in contrast with the surface channel of a conventional device. Another publication entitled The Junction MOS (JMOS) Transistor--A High Speed Transistor For VLSI, by E. Sun et al. (IEDM Digest, 1980, pages 791-794) discloses a MOS device using a layered N-P P-junction structure beneath a MOS gate region. The art has heretofore not exhaustively investigated the origin of threshold voltage in FETs and the reasons for variation of threshold voltage with device characteristics. Accordingly, the art has heretofore not provided an FET design which minimizes variations of threshold voltage by eliminating those characteristics which contribute to this variation.
Miniaturization of MOS devices for VLSI and ULSI designs has also created other problems. For example, short channel devices are increasingly prone to breakdown due to well known punch-through and impact ionization effects. In order to prevent such breakdown, short channel devices have employed scaled down input (supply) voltage, for example, 3 V instead of the standard 5 V supplies heretofore employed. However, as is well known to those having skill in the art, decreasing supply voltage causes threshold voltage to become a greater fraction of the supply voltage, thereby reducing device speed and negating the advantage of short channel devices.
Finally, as device density further increases, it has become more difficult to provide ohmic (i.e. non-rectifying) contacts to these devices. Complex contact metallurgy schemes have been developed in an attempt to provide satisfactory, high density ohmic contacts. Complex contact metallurgy creates manufacturing problems and cannot fully compensate for poor ohmic contacts themselves.
In an effort to improve the performance of FET devices, the art has also focused on Semiconductor-On-Insulator (SOI) technology. In SOI technology, the FET devices are formed in a thin monocrystalline semiconductor layer which is formed on an insulating layer. The insulating layer is typically formed on a substrate which may be silicon. In other words, rather than forming active devices in bulk semiconductor, the active devices are formed in a thin semiconductor on insulator layer. In the present state of the art, silicon is most often used for the monocrystalline semiconductor layer in which devices are formed. However, it will be understood by those having skill in the art that other monocrystalline layers such as germanium or gallium arsenide may be used. Accordingly, any subsequent references to silicon will be understood to encompass any semiconductor.
An SOI FET typically includes a source and drain region of a first conductivity type, typically extending the entire depth of the thin silicon film, and a channel region of opposite conductivity between the source and drain regions, with the channel region typically extending the entire depth of the silicon layer.
The first application of SOI technology was silicon-on-sapphire. More recent efforts have been directed towards growing monocrystalline silicon on top of a silicon dioxide layer grown on a silicon wafer. See for example the publications entitled Ultra-High Speed CMOS Circuits In Thin SIMOX Films to Camgar et al. published in Volume 89 of IEDM, pp. 829-832 (1989) and Fabrication of CMOS on Ultrathin SOI Obtained by Epitaxial Lateral Overgrowth and Chemical-Mechanical Polishing to Shahidi et al. published in Volume 90 of IEDM, pp. 587-590, 1990. SOI technology has several potential advantages compared to bulk FET devices. For example, MOS fabrication processes in SOI are compatible with and may be simpler than MOS fabrication processes in bulk silicon. In SOI technology, shallow source and drain regions can be easily obtained and source and drain capacity can be reduced below typical bulk values. Moreover, both P- and N- channel devices may be fabricated without requiring a contra doped tub implant which is necessary for bulk substrate devices. Also, because the devices are formed in a thin silicon layer on an insulating layer, latchup conditions are eliminated and isolation between devices is enhanced. Finally, avalanche breakdown is also eliminated below the drain and source diffusions.
Unfortunately, conventional SOI technology does have a number of problems. A major problem is the need to grow a high quality, monocrystalline silicon film on top of an insulator. Moreover, carrier mobility in the channel region of SOI FETs is reduced from its bulk value due to the increase in the channel dopant concentration which is required to prevent punchthrough and which is needed to accommodate the depletion effects which are required to control the device pinch off properties. Moreover, the depth of the silicon film grown on the insulator must be shallow (i.e. on the order of a 1,000 .ANG. or less) in order to avoid a "kink" in the drain current versus voltage properties of the FET devices. The need for a thin silicon film requires high doping concentrations (on the order of 1E17 or greater) that results in lowering the effective carrier mobility in the channel region. Finally, threshold voltage of typical SOI devices is low, typically around 200 mV. This low value renders SOI devices susceptible to noise induced errors in VLSI operation.